Synchronous DRAM (SDRAM) has a synchronized interface with a memory controller and synchronously responds to the memory controller at a speed of a system bus of a computer. A clock signal of the computer is used to drive an internal finite state machine (FSM) that pipelines incoming commands from the memory controller. Data storage of SDRAM is divided into several banks, allowing the memory controller to simultaneously process several memory access commands that are interleaved among the separate banks This allows higher data access rates than asynchronous DRAM.
Transaction-based memory systems have recently gained attentions for their higher memory capacity, higher bandwidth, and design flexibility. Examples of transaction-based memory systems include a buffer-on-board type (e.g., Intel® Scalable Memory Buffer (SMB)), a hybrid memory cube (e.g., Micron® Hybrid Memory Cube (HMC)), and HP® Gen-Z®.
Unlike synchronous memory systems, a memory controller in a transaction-based memory system does not communicate directly with DRAMs. Instead, the memory controller (i.e., a master controller) of a computer system communicates with a DRAM controller (i.e., a slave controller) asynchronously over a point-to-point link bus, and the DRAM controller communicates with the DRAMs over a memory channel (e.g., double data rate (DDR) memory channel) using memory commands (e.g., DDR memory commands standardized by the Joint Electron Device Engineering Council (JEDEC)). Examples of standard memory commands include activate, read, write, precharge, and refresh. The activate command activates a row in a particular bank. The read and write commands initiate a read and a write burst to an activated row. The precharge command closes an activated row in a particular bank. The refresh command starts a refresh operation. The memory banks are precharged when a refresh command is issued.
In a conventional transaction-based memory system design, a master controller and a slave controller are loosely coupled and exchange little information. The loosely coupled master and slave controllers provide design flexibility and efficient management of the memory system. However, the loose coupling between the master and the controllers may result in non-optimized performance. For example, rank/bank interleaving and row buffer management are handled by a slave controller alone. Due to power and cost concerns, the slave controller may have limited resources including a small buffer and a simple logic. The limited resources on the slave controller may limit its scheduling and row buffer management capabilities. The master controller, on the other hand, may have plenty of resources and buffers that are potentially capable of enhancing the performance of the memory system by overcoming the limited capabilities of the slave controller.